The invention concerns an error testing and diagnostic device for an electronic data processing system comprising at least one processor, one main storage and one maintenance and service processor interconnected by a fast system bus.
The testing of very large scale integrated logic and storage circuits on chips, of which electronic controls, processors and data processing systems consist, is based to a considerable degree on the accessibility (observability, controllability) of the totality of the storage elements (bistable switches, flip-flops) on the chip.
Therefore, up-to-date logic structures and system architecture frequently use what is known as LSSD rules (LSSD=Level Sensitive Scan Design), according to which, for example, a logic subsystem is level sensitive if, and only if, the response to an input signal change in the steady state is independent of circuit and line delays in the logic subsystem (cf. "A Logic Design Structure for LSI Testability" by E. B. Eichelberger - Proceedings of the Design Automation Conference No. 14, 20-22 June 1977, New Orleans, La., pp. 462 to 468).
Based on these LSSD rules, the totality of the storage elements are made observable and controllable in that the master/slave flip-flops, which are logic components and which are also positioned between the logic stages, are interconnected in the test mode as one shift register chain or several such chains. These chains are used to shift test patterns into the innards of the logic and to shift out result patterns.
The shift register chains may also be used to shift complete flip-flop or register status information into or out of complex logic groups, such as chips or modules, which are separated from each other with regard to their packaging. This shift register approach has the advantage that only relatively few input/output terminals are required and that there is a high degree of flexibility between the various packaging levels if all first packaging level shift register chains are connected to a common second packaging level shift register chain, etc., without adversely affecting the logic design in the chip.
Owing to the serial information transfer for performing tests by shifting in test patterns and shifting out result patterns, this shift register concept is highly time-consuming in the test mode. Its multi-channel feature makes this concept also relatively susceptible to noise and quite expensive, as the shift register stages consist of master/slave flip-flops, whose slave flip-flops are not required during normal operation. As a result of this disadvantage, the logic density on the chip is less than it could be if only master flip-flops were used.